1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a high speed and low parasitic capacitance semiconductor device including a vertical transistor and a heterojunction bipolar transistor, and a method for fabricating such the device.
2. Description of the Related Art
A high speed bipolar transistor may be realized by increasing cut-off frequency fT as well as reducing the parasitic capacitance and parasitic resistance. A typical parasitic capacitance includes collector-base capacitance CCB. A pn junction capacitance per unit junction area may be determined almost with a relatively lower one between impurity concentrations in p-type and n-type regions. Thus, capacitance CCB can be determined in accordance with a design for the collector concentration. When focusing attention only on the parasitic capacitance, therefore, it is desirable to reduce the collector concentration as low as possible.
On the other hand, however, the collector capable of improving cut-off frequency fT may have a relatively higher concentration to prevent the electric field from decreasing inside the depletion layer between the collector and base at high current operation. Thus, the contrary requests must be satisfied at the same time.
Any conventional technology has not responded such the requests and still includes the following disadvantages. A base region on which an emitter is formed directly is hereinafter referred to as an intrinsic base and a peripheral region thereof is called an outer base region.
FIG. 24 is a vertical cross sectional view showing a semiconductor device according to a first related art. The device includes p type silicon substrate 1, n+ buried layer 2a, adjacent p+ buried layer 2b, epitaxial silicon collector layer 3, silicon oxide 4 formed by LOCOS (local oxidation of silicon) and collector lead-out region 5. The device also includes silicon oxide 6, polysilicon base electrode 7, silicon oxide 8, outer base region 10, intrinsic base 11, second collector region 12, polysilicon emitter electrode 13 and single crystalline emitter region 14. The device further includes silicon oxide 15, aluminum alloy emitter electrode 16a, aluminum alloy base electrode 16b, aluminum alloy collector electrode 16c, first aperture 101, second aperture 102 and third aperture 103.
A vertical bipolar transistor is fabricated with emitter 14, intrinsic base 11 and second collector 12, in the above semiconductor device, which are lead out through the electrodes isolated by silicon oxides 6, 8 and 15.
Second collector 12 located directly beneath outer base 10 has a high collector concentration equal to that of the region directly beneath intrinsic base 11 in this semiconductor device. Whereas the high speed may be achieved to a certain extent, therefore, the collector-base capacitance intends to increase.
FIG. 25 is a vertical cross sectional view showing another semiconductor device according to the first related art. Description for the same portions as those in FIG. 24 may be omitted in FIG. 25 with giving the same reference numerals. Note that a feature of collector 12 greatly differs from that in FIG. 24.
The collector concentration directly beneath outer base 10 in the semiconductor device is controlled lower than that of the region directly beneath intrinsic base 11. However, low concentration collector region 3 is interposed between high concentration collector region 12 directly beneath intrinsic base 11 and n+ buried layer 2a. Therefore, cut-off frequency fT may decrease even if the collector-base capacitance is small.
FIG. 26 is a vertical cross sectional view showing a semiconductor device according to a second related art. The device includes p type silicon substrate 1, n+ buried layer 2a, adjacent p+ buried layer 2b, epitaxial silicon collector layer 3, LOCOS silicon oxide 4 and collector lead-out region 5. The device also includes silicon oxide 6, polysilicon base electrode 7, silicon oxide 8, outer base 10, intrinsic base 11, second collector region 12, polysilicon emitter electrode 13 and single crystalline emitter region 14. The device further includes silicon oxide 15, aluminum alloy emitter electrode 16a, aluminum alloy base electrode 16b and aluminum alloy collector electrode 16c. 
A vertical bipolar transistor is fabricated with emitter 14, intrinsic base 11 and second collector 12, in the above semiconductor device, which are lead out through the electrodes isolated by silicon oxides 6, 8 and 15.
In this structure, single crystalline base 11 is epitaxially grown whole over Si collector region 12. Whereas there is no region called outer base 10, a portion directly beneath the emitter may be considered as the intrinsic base. Thus, the collector located direct beneath a peripheral base region of the intrinsic base may also have a high concentration.
FIG. 27 is a vertical cross sectional view showing a semiconductor device according to a third related art. The device includes p-silicon substrate 1, n+ buried layer 2a, adjacent p+ buried layer 2b, epitaxial silicon collector layer 3, LOCOS silicon oxide 4 and collector lead-out region 5. The device also includes a silicon oxide 6, polysilicon base electrode 7, silicon oxide 24, intrinsic base 11, single crystalline Si intrinsic base layer 21, polycrystalline Si layer 22, single crystalline emitter region 23 and silicon oxide 25. The device further includes second collector region 12, polysilicon emitter electrode 13, silicon oxide 15, aluminum alloy emitter electrode 16a, aluminum alloy base electrode 16b and aluminum alloy collector electrode 16c. The device also includes aperture 201 for making silicon oxide 6 contact with single crystalline Si intrinsic base layer 21 and polycrystalline Si layer 22, and aperture 202 for making polysilicon emitter electrode 13 and single crystalline emitter region 23 contact with intrinsic base 21 and polycrystalline Si layer 41.
Whereas aperture 202 must be formed by aligning with previously formed aperture 201 in the first and second related arts, the aperture may only be formed once according to the third related art, whereby miniaturization of the transistor may be achieved.
The above-described related arts, however, can not realize both the low collector concentration for reducing the parasitic capacitance and the high collector concentration for improving the cut-off frequency fT simultaneously.
An object of the present invention is to provide a semiconductor device capable of satisfying the contrary requests to achieve both the low collector concentration for reducing the parasitic capacitance and the high collector concentration for improving cut-off frequency fT simultaneously.
The present invention is provided with a method for fabricating a semiconductor device comprising the steps of: forming a silicon material having a high concentration buried layer and a low concentration surface region; forming a single layer or multi-layered film on the surface of the silicon material; opening an aperture in the film by means of photolithography and dry etch; implanting phosphorous ions into the silicon material to form a first collector region adjacent to the buried layer before removing the photoresist; implanting boron ions into the surface of the silicon material to form an intrinsic base; implanting phosphorous ions selectively into the silicon material to form a second collector region between the intrinsic base and the first collector region with using the film used to form the aperture as the mask; and disposing a polysilicon emitter electrode for diffusing the dopant from the polysilicon emitter electrode into the intrinsic base region to form a single crystalline emitter region.
The present invention is also provided with a method for fabricating a semiconductor device including a bipolar transistor having a base formed by epitaxial growth or ion implantation, wherein the bipolar transistor has an epitaxial silicon collector layer, a base region directly under an emitter defined as an intrinsic base and a peripheral region thereof defined as an outer base region, the method comprising the steps of: implanting ions into the collector layer to form a high concentration collector region at a location close to a buried region with using a photoresist used to form an aperture; forming the base region; and implanting ions into the collector layer to form a high concentration collector region directly beneath the base region.
The present invention is further provided with a method for fabricating a semiconductor device comprising the steps of: forming a silicon material having a high concentration buried layer and a low concentration surface region; forming a first insulating film, a polysilicon base electrode and a photoresist on the silicon material; patterning the photoresist; opening an aperture in the polysilicon base electrode and the insulating film by anisotropic dry etching; implanting phosphorous ions to form a first collector region adjacent to the buried layer; growing a boron doped silicon by non-selective epitaxial growth; forming a single crystalline intrinsic base on the silicon material; forming a polycrystalline silicon on a region other than the intrinsic base; covering the surface with a second insulating film; patterning a photoresist and performing anisotropic dry etching to open an aperture on the intrinsic base; and implanting phosphorous ions to form a second collector region on the first collector region.
The present invention is also provided with a method for fabricating a semiconductor device comprising the steps of: forming a silicon material having a high concentration buried layer and a low concentration surface region; forming a first insulating film on the silicon material; depositing a polysilicon base electrode; removing the undesired polysilicon by photolithography and anisotropic dry etching; covering the whole surface with a second insulating film having a different substance from that of the first insulating film; opening an aperture in the second insulating film and the polysilicon base electrode; implanting phosphorous ions to form a first collector region; forming a third insulating film having the same substance as that of the second insulating film; etching back the third insulating film by a thickness deposited just before to expose the first insulating film; etching the first insulating film in the lateral direction to expose the silicon material and a lower surface of the polysilicon base electrode; forming an intrinsic base and a polycrystalline outer base for connecting the intrinsic base with the polysilicon base electrode by selective crystal growth; and implanting phosphorous ions to form a second collector region.
The present invention is provided with a semiconductor device fabricated by any one of the methods described above.
In the semiconductor device according to the present invention, a base region on which an emitter is formed directly is referred to as an intrinsic base and a peripheral region thereof is called an outer base region. An effective thickness of a collector region in the bipolar transistor that is formed by an epitaxial growth, ion implantation and the like is defined as Wc which means a distance between the intrinsic base and buried layer 2a. A thickness of the intrinsic base is defined as WB. A total thickness originated from the junction interface between the outer base and the collector region through various films disposed thereon to a lower surface of the polysilicon emitter is defined as t. The t is expressed in FIG. 1 as a total thickness including the depth of outer base 10, the film thickness of polysilicon base electrode 7 and the film thickness of silicon oxide 8. This is a transistor structure defined by t less than WB+Wc.
The device may be produced by implanting ions into the epitaxial collector layer to form a high concentration collector region at a location close to a buried region with using a photoresist used to form an aperture, and then implanting ions into the collector layer to form a high concentration collector region directly beneath the base region after forming the base region. Thus performing twice ion implantations may realize the improvement of cut-off frequency fT and the reduction of base-collector capacitance CCB at the same time.
With respect to the heterojunction bipolar transistor in which the collector region consists of Si and the intrinsic base consists of an Sixe2x80x94Ge alloy, a boron-containing region may be formed at an interface between SiGe/Si collector in accordance with a pretreatment before SiGe/Si base growth. In this case, an addition of a dopant with an opposite conductivity for compensating the boron-containing region may be performed after forming the base to prevent an energy barrier from generating in the heterointerface.
Other features and advantages of the invention will be apparent from the following description of the preferred embodiments.